Problem:

It is experienced that HDL synthesis tools has big impact on the resource usage of the same design on the same target device. However it is not always clear what is the reason for this difference, and how it can be influenced during coding.

 

Action:

Activities with the following phases could be started: 

- Create/start with 2-3 example designs

- Compile it with different synthesis tools

- Compare results, analyse reason of the differences

 

Result:

Following achievements are expected: 

- Comparative study on the synthesis tools’ performance

- Suggestions for design rules for minimal resource usage

 

Ericsson dependence: no

 

Tags: FPGA, synthesis tools